The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Mar. 05, 2018
Applicant:
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Inventors:
Makoto Kitagawa, Kanagawa, JP;
Yoshiyuki Shibahara, Tokyo, JP;
Haruhiko Terada, Kanagawa, JP;
Yotaro Mori, Kanagawa, JP;
Assignee:
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); G11C 13/003 (2013.01); H01L 27/2436 (2013.01); G11C 2213/71 (2013.01); G11C 2213/79 (2013.01);
Abstract
In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.