The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

May. 15, 2019
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Te-Yin Chen, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/762 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 29/40 (2006.01); H01L 21/311 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10894 (2013.01); H01L 21/26513 (2013.01); H01L 21/308 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/823437 (2013.01); H01L 27/10897 (2013.01); H01L 29/401 (2013.01);
Abstract

The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a substrate having a memory cell region and a peripheral region, wherein the memory cell region has at least one first shallow trench isolation and the peripheral region has at least one second shallow trench isolation; a plurality of gates in the first shallow trench isolation; a first semiconductor layer in the peripheral region; a first insulating layer covering the substrate in the memory cell region; a crystalline overlayer in the memory cell region and a doped portion of the substrate below the crystalline overlayer; and a second semiconductor layer on a portion of the first insulating layer, wherein a top surface of the first semiconductor layer and a top surface of the second semiconductor layer are coplanar.


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