The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

Mar. 14, 2019
Applicant:

The Regents of the University of California, Oakland, CA (US);

Inventors:

Ryan Kastner, La Jolla, CA (US);

Armaiti Ardeshiricham, La Jolla, CA (US);

Wei Hu, La Jolla, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/327 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/33 (2020.01);
Abstract

Disclosed are devices, apparatuses, systems, computer readable media, and methods for improving the security of circuitry designs using HDL code. In one aspect a method is disclosed. the method includes receiving a hardware design language (HDL) representation of a circuit; inserting flow tracking into the HDL representation, wherein the flow tracking adds one or more security labels that are tracked throughout the circuit; and generating an enhanced HDL representation of the circuit, wherein the enhanced HDL representation comprises the HDL representation and the flow tracking, wherein the enhanced representation including the one or more security labels that are tracked throughout the circuit enables a security determination a model for tracking timing-based information flows through HDL code is disclosed. The disclosed technology is used to verify security properties on a variety of equipment including crypto cores, bus architectures, caches and arithmetic modules.


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