The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

Dec. 18, 2017
Applicant:

Nuvoton Technology Corporation, Hsinchu Science Park, TW;

Inventor:

Ilan Margalit, Tel-Aviv, IL;

Assignee:

NUVOTON TECHNOLOGY CORPORATION, Hsinchu Science Park, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 12/14 (2006.01); G06F 12/16 (2006.01); G06F 21/00 (2013.01); G06F 21/57 (2013.01); G06F 21/54 (2013.01); G06F 21/55 (2013.01);
U.S. Cl.
CPC ...
G06F 21/577 (2013.01); G06F 21/54 (2013.01); G06F 21/552 (2013.01); G06F 2221/034 (2013.01); G06F 2221/2113 (2013.01); G06F 2221/2137 (2013.01);
Abstract

A security system dynamically, depending on processor core execution flow, controls fault injection countermeasure circuitry protect processor core from fault injection attacks. Includes a processor core which, when in use, executes instructions and concurrently, generates, in real time, output indications of instructions to be executed; a fault injection detector having selectable sensitivity levels; and a sensitivity level control module operative, in real time, to receive the output indications, select a next sensitivity level using sensitivity level selection logic which receives the output indications as inputs, and set the fault injection detector to the next sensitivity level, thereby to provide fault injection countermeasure circuitry which is differentially sensitive, when protecting the processor core from fault injection attacks, depending on the output indications of the instructions, and/or avoids false alarms which would result if processor core protection were provided at a sensitivity level unrelated to the output indications of the instructions.


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