Semiconductor integrated circuit, a/d converter, delta sigma-type a/d converter, incremental delta sigma-type a/d converter, and switched capacitor

Abstract

According to one embodiment, a semiconductor integrated circuitincludes a sample and hold circuit and a clock generation circuit. The sample and hold circuit has a device with a first withstand voltage and a device with a second withstand voltage that is higher than the first withstand voltage. The clock generation circuit generates a first clock signal to be supplied to the first withstand voltage device and generates a second clock signal to be supplied to the second withstand voltage device based on the first clock signal. The clock generation circuit has a delay adjustment circuit that performs adjustment to delay the second clock signal and bring a phase of the second clock signal close to a phase of the first clock signal in the generation of the second clock signal.