The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2021
Filed:
Dec. 04, 2019
University of Electronic Science and Technology of China, Chengdu, CN;
Hua Fan, Chengdu, CN;
Chen Wang, Chengdu, CN;
Peng Lei, Chengdu, CN;
Dainan Zhang, Chengdu, CN;
Quanyuan Feng, Chengdu, CN;
Lang Feng, Chengdu, CN;
Xiaopeng Diao, Chengdu, CN;
Dagang Li, Chengdu, CN;
Kelin Zhang, Chengdu, CN;
Daqian Hu, Chengdu, CN;
Yuanjun Cen, Chengdu, CN;
UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, Chengdu, CN;
Abstract
A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors C*, C* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR ADC.