The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Nov. 01, 2018
Applicants:

Brian Paul Wagner, Baltimore, MD (US);

Christopher F. Kirby, Gambrills, MD (US);

Michael Rennie, Ashland, VA (US);

James T. Kelliher, Elkridge, MD (US);

Khyhouth Lim, Baltimore, MD (US);

Inventors:

Brian Paul Wagner, Baltimore, MD (US);

Christopher F. Kirby, Gambrills, MD (US);

Michael Rennie, Ashland, VA (US);

James T. Kelliher, Elkridge, MD (US);

Khyhouth Lim, Baltimore, MD (US);

Assignee:

NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01); H01L 39/24 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76891 (2013.01); H01L 21/02063 (2013.01); H01L 21/02068 (2013.01); H01L 21/76826 (2013.01); H01L 23/53285 (2013.01); H01L 23/53295 (2013.01); H01L 39/2406 (2013.01); H01L 21/02697 (2013.01);
Abstract

A method is provided of forming a superconductor device interconnect structure. The method comprises forming a first dielectric layer overlying a substrate and forming a superconducting interconnect element in the first dielectric layer. The superconducting interconnect element includes a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The superconductor device interconnect structure is moved into a dielectric deposition chamber. The method further comprises performing a cleaning process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer, and depositing a second dielectric layer over the first interconnect layer in the dielectric deposition chamber.


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