The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Feb. 08, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Chandrasekhar S Thyamagondlu, Sunnyvale, CA (US);

Darren Jue, Sunnyvale, CA (US);

Tao Yu, Campbell, CA (US);

John West, Erie, CO (US);

Hanh Hoang, Hayward, CA (US);

Ravi Sunkavalli, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/1081 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 2212/621 (2013.01); G06F 2213/28 (2013.01);
Abstract

Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.


Find Patent Forward Citations

Loading…