The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Feb. 14, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Nagendra K. Gurram, Bangalore, IN;

Saravanan Sethuraman, Bangalore, IN;

Edgar R. Cordero, Round Rock, TX (US);

Anuwat Saetow, Austin, TX (US);

Diyanesh B. Chinnakkonda Vidyapoornachary, Bangalore, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06F 13/16 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/5044 (2013.01); G06F 9/3891 (2013.01); G06F 9/5066 (2013.01); G06F 9/5077 (2013.01); G06F 13/1663 (2013.01); G06F 2209/501 (2013.01); G06F 2209/506 (2013.01);
Abstract

A method for configuring hardware within a computing system. The method includes one or more computer processors identifying information respectively associated with a plurality of hardware resources within a portion of a computing system. The method further includes determining whether a set of memory modules of differing performance ratings are operatively coupled to a shared bus fabric. The method further includes responding to determining that the set of memory modules of differing performance ratings is operatively coupled to the shared bus fabric by configuring a subsystem to selectively access respective groups of memory modules within the set of memory modules based on a performance rating corresponding to a respective group of memory modules.


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