The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Dec. 19, 2017
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Sean M. Reynolds, Cupertino, CA (US);

Gokul V. Ganesan, Santa Clara, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 9/3836 (2013.01); G06F 9/3855 (2013.01); G06F 9/3867 (2013.01);
Abstract

Techniques are disclosed relating to selection circuitry configured to select instruction operations to issue to one or more execution circuits of a processor. In some embodiments, an apparatus includes a plurality of execution circuits configured to perform one or more instruction operations. The apparatus may further include a plurality of instruction queues configured to store information indicative of the one or more instruction operations. In some embodiments, the apparatus may include a selection circuit configured to select a first plurality of instruction operations from a first instruction queue. The selection circuit may be configured to select a first instruction operation from the first plurality of instruction operations to issue to a first execution circuits. Further, the selection circuit may be configured to select a predesignated instruction operation of the first plurality of instruction operations to issue to a second execution circuit in response to a determination that no instruction operations in a second instruction queue are available to issue.


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