The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Aug. 23, 2018
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Peter F. Holland, Los Gatos, CA (US);

Christopher P. Tann, San Jose, CA (US);

Malcolm D. Gray, Sunnyvale, CA (US);

Hari Ganesh R. Thirunageswaram, Fremont, CA (US);

Kristan Jon Monsen, Los Altos, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/36 (2006.01); G06F 1/32 (2019.01); G06T 1/60 (2006.01); G09G 5/00 (2006.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01); G06T 15/00 (2011.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G09G 5/363 (2013.01); G09G 2330/023 (2013.01); G09G 2360/12 (2013.01);
Abstract

The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).


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