The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10979531 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 13, 2021

Filed:

Jan. 31, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Seetharami Seelam, Chappaqua, NY (US);

Minsik Cho, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/08 (2006.01); H04L 12/911 (2013.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
H04L 67/32 (2013.01); H04L 41/12 (2013.01); H04L 47/829 (2013.01);
Abstract

Various embodiments are provided for using pessimistic scheduling for topology optimized workload placement by a processor in a computing environment. An excessive amount of computing resources may be requested (e.g., a pessimistic request) to execute a workload as compared to a required amount of the computing resources to execute the workload. The workload may be assigned to a selected configuration of the excessive amount of computing resources and releasing a remaining amount of the excessive amount of computing resources.


Find Patent Forward Citations

Seelam, Seetharami. (2021). Pessimistic scheduling for topology optimized workload placement (U.S. Patent No. 10979531). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10979531

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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