The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Apr. 01, 2019
Applicant:

Excelero Storage Ltd., Tel Aviv, IL;

Inventors:

Yaniv Romem, Jerusalem, IL;

Omri Mann, Jerusalem, IL;

Ofer Oshri, Kfar Saba, IL;

Kirill Shoikhet, Raanana, IL;

Assignee:

Excelero Storage Ltd., Tel Aviv, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/08 (2006.01); G06F 16/30 (2019.01); G06F 16/00 (2019.01); G06F 3/06 (2006.01); G06F 12/109 (2016.01);
U.S. Cl.
CPC ...
H04L 67/1097 (2013.01); G06F 3/061 (2013.01); G06F 3/067 (2013.01); G06F 3/0665 (2013.01); G06F 12/109 (2013.01); G06F 16/00 (2019.01); G06F 16/30 (2019.01); G06F 2212/1024 (2013.01); G06F 2212/154 (2013.01); G06F 2212/163 (2013.01); G06F 2212/657 (2013.01);
Abstract

A system and method for improving multi-core processor access to storages, the method including: assigning a unique memory space within a memory to each of a plurality of processor cores; initiating a shared queue pair (QP), comprising a shared send queue and a shared receive queue, between the plurality of processor cores and at least a storage, wherein the shared queue is accessible by the plurality of processor cores; sending an instruction on the shared send queue from a first core of the plurality of processor cores to the storage, the instruction comprising an interrupt destination on a memory space assigned to the first core; and receiving an interrupt at the interrupt destination from the storage in response to the instruction, wherein the interrupt is generated for the first core.


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