The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Jan. 21, 2019
Applicant:

Nanobridge Semiconductor, Inc., Tokyo, JP;

Inventors:

Ryusuke Nebashi, Tokyo, JP;

Toshitsugu Sakamoto, Tokyo, JP;

Makoto Miyamura, Tokyo, JP;

Yukihide Tsuji, Tokyo, JP;

Ayuka Tada, Tokyo, JP;

Xu Bai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2020.01); H01L 25/00 (2006.01); H03K 19/17736 (2020.01); G11C 13/00 (2006.01); H03K 19/17704 (2020.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17744 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0069 (2013.01); H03K 19/1776 (2013.01); H03K 19/17708 (2013.01);
Abstract

A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.


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