The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Sep. 16, 2019
Applicant:

Sharp Kabushiki Kaisha, Sakai, JP;

Inventors:

Junichi Morinaga, Sakai, JP;

Hikaru Yoshino, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1343 (2006.01); G02F 1/1333 (2006.01); H01L 51/56 (2006.01);
U.S. Cl.
CPC ...
H01L 27/3258 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/136286 (2013.01); H01L 27/1251 (2013.01); H01L 27/3244 (2013.01); H01L 27/3262 (2013.01); H01L 27/3276 (2013.01); H01L 27/3279 (2013.01); H01L 51/56 (2013.01);
Abstract

An active matrix substrate includes a first TFT of a peripheral circuit and a second TFT arranged in each pixel, wherein: the first TFT is a top gate or double gate TFT that includes an upper gate electrode on a portion of a first oxide semiconductor layer with a gate insulating layer interposed therebetween; the second TFT is a bottom gate TFT that includes a second lower gate electrode arranged on the substrate side of a second oxide semiconductor layer with a lower insulating layer interposed therebetween and includes no gate electrode on the second oxide semiconductor layer; the second TFT including: an island-shaped insulator layer that is arranged on a portion of the second oxide semiconductor layer so as to overlap with at least a portion of the second lower gate electrode, as seen from a direction normal to the substrate; an upper insulating layer that is arranged on the second oxide semiconductor layer and the island-shaped insulator layer; and a source electrode that is arranged on the upper insulating layer, wherein: a portion of the second oxide semiconductor layer that does not overlap with the island-shaped insulator layer is a low resistance region that has a lower specific resistance than a portion thereof that overlaps with the island-shaped insulator layer; and in an intersection between a source bus line and a gate bus line, the lower insulating layer and the upper insulating layer are located between these bus lines.


Find Patent Forward Citations

Loading…