The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2021
Filed:
Jul. 26, 2019
Fuji Electric Co., Ltd., Kawasaki, JP;
Morio Iwamizu, Matsumoto, JP;
Shigeyuki Takeuchi, Matsumoto, JP;
FUJI ELECTRIC CO., LTD., Kawasaki, JP;
Abstract
Provided is a semiconductor device capable of reducing a mounting area. A semiconductor device () includes a semiconductor element () and a control element () arranged on a front surface () of the semiconductor element (). The semiconductor element () includes a semiconductor substrate (SB) including a first region ARand a second region ARadjacent to each other, a first MOS transistor (Tr) provided is the first region (AR), and a second MOS transistor (Tr) provided in the second region (AR). A first drain region () of the first MOS transistor (Tr) is connected to a second drain region () of the second MOS transistor (Tr). The control element () turns on and off the first MOS transistor (Tr) and the second MOS transistor (Tr).