The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2021
Filed:
Jan. 30, 2019
Applicant:
Delta Electronics, Inc., Taoyuan, TW;
Inventors:
Liang-Cheng Wang, Taoyuan, TW;
Shiau-Shi Lin, Taoyuan, TW;
Assignee:
DELTA ELECTRONICS, INC., Taoyuan, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 28/40 (2013.01); H01L 2224/214 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/1426 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01);
Abstract
A package structure includes a substrate, a first capacitor, a System on Chip unit and a wiring layer. The first capacitor is provided on the substrate. The System on Chip unit is bonded with the first capacitor in a first dielectric layer. The wiring layer is configured to electrically couple the first capacitor and the System on Chip unit. The wiring layer is provided on the first dielectric layer through a second dielectric layer.