The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Oct. 17, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yoshiyuki Kawashima, Tokyo, JP;

Takashi Hashimoto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 23/522 (2006.01); H01L 27/11517 (2017.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/762 (2006.01); H01L 49/02 (2006.01); H01L 27/11573 (2017.01); H01L 29/94 (2006.01); H01L 27/12 (2006.01); H01L 27/08 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/762 (2013.01); H01L 21/76877 (2013.01); H01L 23/53295 (2013.01); H01L 27/11517 (2013.01); H01L 27/11573 (2013.01); H01L 27/1207 (2013.01); H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 29/94 (2013.01); H01L 27/0629 (2013.01); H01L 27/0805 (2013.01);
Abstract

This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.


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