The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2021
Filed:
Mar. 17, 2017
Xerox Corporation, Norwalk, CT (US);
Markus Rudolf Silvestri, Fairport, NY (US);
Kamran Uz Zaman, Pittsford, NY (US);
Christopher P. Caporale, Rochester, NY (US);
Jimmy E. Kelly, Rochester, NY (US);
John M. Scharr, Canandaigua, NY (US);
Alberto Rodriguez, Webster, NY (US);
Dennis J. Prosser, Walworth, NY (US);
XEROX CORPORATION, Norwalk, CT (US);
Abstract
A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.