The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Nov. 13, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Rajdeep Gautam, Yokohama, JP;

Hardwell Chibvongodze, Hiratsuka, JP;

Ken Oowada, Fujisawa, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/28 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 11/5635 (2013.01); G11C 16/10 (2013.01); G11C 16/28 (2013.01); G11C 16/3427 (2013.01);
Abstract

Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.


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