The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

May. 10, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Ryoji Hashimoto, Tokyo, JP;

Keisuke Matsumoto, Tokyo, JP;

Nhat Van Huynh, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 9/00 (2006.01); G06T 1/60 (2006.01); H04N 19/423 (2014.01); H04N 19/80 (2014.01); H04N 19/85 (2014.01); H04N 19/42 (2014.01); H04N 19/176 (2014.01); H04N 19/86 (2014.01); H04N 19/625 (2014.01);
U.S. Cl.
CPC ...
G06T 9/00 (2013.01); G06T 1/60 (2013.01); H04N 19/176 (2014.11); H04N 19/42 (2014.11); H04N 19/423 (2014.11); H04N 19/80 (2014.11); H04N 19/85 (2014.11); H04N 19/86 (2014.11); H04N 19/625 (2014.11);
Abstract

The present invention provides a semiconductor device enabling efficient compression without increasing the circuit size and a processing method using the semiconductor device. According to an embodiment, an image processor includes: a coding circuit to perform image processing on a target image divided into a plurality of tiles, the image processing being performed on each of the tiles; a determination circuit to determine whether a tile boundary is included in the area of an image block serving as a unit of compression of the target image; and a compression circuit to compress the image block image-processed by the coding circuit, according to a determination result of the determination circuit.


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