The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2021
Filed:
Dec. 23, 2019
Xilinx, Inc., San Jose, CA (US);
Jeffrey M. Arnold, San Diego, CA (US);
Stephen L. Bade, Lindon, UT (US);
Srinivas Beeravolu, Los Gatos, CA (US);
Chukwuweta Chukwudebe, Milpitas, CA (US);
Anindita Patra, Fremont, CA (US);
Nabeel Shirazi, Saratoga, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.