The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2021

Filed:

Nov. 08, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Christopher Y. Karman, Frederick, CO (US);

Vidya Gopalakrishnan, San Jose, CA (US);

Ramesh Barukula, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/4401 (2018.01); G06F 13/42 (2006.01); G06F 9/445 (2018.01);
U.S. Cl.
CPC ...
G06F 9/4411 (2013.01); G06F 13/4282 (2013.01); G06F 9/44505 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Some examples described herein provide for dynamically reconfiguring a base address register (BAR) of a Peripheral Component Interconnect Express (PCIe) configuration space. In an example, information relating to a BAR of a PCIe configuration space is written to a PCIe extended configuration space of the PCIe configuration space, which is read, by a dynamic BAR module. Respective values are written, by the dynamic BAR module, to bits of the BAR based on the information. After writing by the dynamic BAR module, a set value is attempted to be written to each of address bits of the BAR. Writing the set value to an address bit of the BAR is prevented when the address bit is set to a predefined value. After attempting to write, a read value is read from the bits of the BAR. A base address of memory is written to the BAR based on the read value.


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