The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

May. 21, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Rishubh Khurana, New Delhi, IN;

Tanmay Neema, Bengaluru, IN;

Kanak Chandra Das, Gayeshpur, IN;

Atul Kumar Agrawal, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/24 (2006.01); H03K 17/22 (2006.01); H03K 17/30 (2006.01);
U.S. Cl.
CPC ...
H03K 17/22 (2013.01); G06F 1/24 (2013.01); H03K 17/30 (2013.01);
Abstract

An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.


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