The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Nov. 08, 2018
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Zhaohui He, Austin, TX (US);

Rahul Singh, Austin, TX (US);

Ruoxin Jiang, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/217 (2006.01); H03F 3/45 (2006.01); H03F 3/187 (2006.01); H03F 1/02 (2006.01); H03F 1/32 (2006.01);
U.S. Cl.
CPC ...
H03F 3/2171 (2013.01); H03F 1/0205 (2013.01); H03F 1/0211 (2013.01); H03F 1/3205 (2013.01); H03F 1/3211 (2013.01); H03F 3/187 (2013.01); H03F 3/2173 (2013.01); H03F 3/45215 (2013.01); H03F 3/45475 (2013.01); H03F 3/45672 (2013.01); H03F 2200/03 (2013.01); H03F 2200/129 (2013.01); H03F 2200/135 (2013.01); H03F 2200/264 (2013.01); H03F 2200/267 (2013.01); H03F 2200/351 (2013.01); H03F 2200/462 (2013.01); H03F 2200/471 (2013.01); H03F 2203/45116 (2013.01); H03F 2203/45512 (2013.01); H03F 2203/45528 (2013.01);
Abstract

A Class-D amplifier having a low power dissipation mode includes first and second independent output stages that receive respective first and second level power supply voltages for driving a load coupled to the amplifier output during respective first and second operating modes. Bypass switches are controllable to disconnect the second output stage from the output during the first operating mode and to connect the second output stage to the output during the second operating mode. The operating modes are selected based on the amplifier output power level. First and second independent pre-driver stages receive the respective first and second level power supply voltages for driving the respective first and second independent output stages. During the second operating mode the first pre-driver stage is placed into a low power dissipation state and during the first operating mode the second pre-driver stage is placed into a low power dissipation state.


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