The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Mar. 15, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sung-Ho Eun, Seoul, KR;

Daehwan Kang, Seoul, KR;

Sungwon Kim, Hwaseong-si, KR;

Youngbae Kim, Seoul, KR;

Seokjae Won, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); H01L 27/249 (2013.01); H01L 27/2463 (2013.01); H01L 45/06 (2013.01); H01L 45/1226 (2013.01); H01L 45/1253 (2013.01); H01L 45/141 (2013.01); H01L 45/1608 (2013.01); H01L 45/1683 (2013.01);
Abstract

A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines.


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