The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Oct. 06, 2016
Applicant:

Flir Systems, Inc., Wilsonville, OR (US);

Inventors:

Richard E. Bornfreund, Santa Barbara, CA (US);

Joseph H. Durham, Santa Barbara, CA (US);

Assignee:

FLIR SYSTEMS, INC., Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/027 (2006.01); H01L 21/3213 (2006.01); H01L 23/00 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1465 (2013.01); H01L 21/0272 (2013.01); H01L 21/32133 (2013.01); H01L 21/32136 (2013.01); H01L 23/544 (2013.01); H01L 24/11 (2013.01); H01L 27/1469 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14689 (2013.01); H01L 24/13 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/119 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/11622 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13109 (2013.01); H01L 2224/14135 (2013.01); H01L 2224/14136 (2013.01); H01L 2224/14177 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81193 (2013.01);
Abstract

Systems and methods may be provided for coupling together semiconductor devices. One or more of the semiconductor devices may be provided with an array of bump contacts formed in an etch back process. The bump contacts may be indium bumps. The indium bumps may be formed by depositing a sheet of indium onto a surface of a device substrate, depositing and patterning a layer of photoresist over the indium layer, and selectively etching the indium layer to the surface of the substrate using the patterned photoresist layer to form the indium bumps. The substrate may be an infrared detector substrate. The infrared detector substrate may be coupled to a readout integrated circuit substrate using the bumps.


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