The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Feb. 15, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Yoshitaka Otsu, Yokkaichi, JP;

Kei Nozawa, Yokkaichi, JP;

Yashushi Doda, Yokkaichi, JP;

Naoto Hojo, Yokkaichi, JP;

Yoshinobu Tanaka, Yokkaichi, JP;

Koichi Ito, Yokkaichi, JP;

Zhiwei Chen, Yokkaichi, JP;

Yusuke Ikawa, Yokkaichi, JP;

Takeshi Kawamura, Yokkaichi, JP;

Ryoichi Ehara, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 27/11556 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11526 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 29/40117 (2019.08); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01);
Abstract

A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers. The dielectric support pillar structures may be formed before or after formation of stepped surfaces in the alternating stack.


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