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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10971401 B1

PDFFull Text
Date of Patent:
Apr. 06, 2021

Filed:

Oct. 04, 2019

Systems and methods for precision fabrication of an orifice within an integrated circuit

Applicant:

Cerebras Systems Inc., Los Altos, CA (US);

Inventor:

Jean-Philippe Fricker, Los Altos, CA (US);

Assignee:

Cerebras Systems Inc., Los Altos, CA (US);

Attorney:

Jeffrey Schox

Primary Examiner:

Anita K Alanko

Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 21/768 (2006.01); B23K 26/384 (2014.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/02019 (2013.01); H01L 21/0475 (2013.01); H01L 21/3043 (2013.01); H01L 21/30604 (2013.01); H01L 21/76802 (2013.01); B23K 26/384 (2015.10); H01L 21/3065 (2013.01); H01L 21/3105 (2013.01);
Abstract

A method for fabricating an orifice in a semiconductor which can include: removing a first depth of the semiconductor using a first material removal technique and removing a second depth of the semiconductor using a second material removal technique. The method can optionally include: adding a sacrificial layer of material and reducing a depth of the semiconductor by a friction-based material removal technique. In examples, the method fabricates a wafer-scale processor with a set of fastening features.

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Fricker, Jean-Philippe. (2021). Systems and methods for precision fabrication of an orifice within an integrated circuit (U.S. Patent No. 10971401). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10971401

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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