The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2021
Filed:
Feb. 26, 2019
Applicant:
Furukawa Electric Co., Ltd., Tokyo, JP;
Inventors:
Yusuke Goto, Tokyo, JP;
Hirotoki Yokoi, Tokyo, JP;
Assignee:
FURUKAWA ELECTRIC CO., LTD., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); B23K 26/38 (2014.01); H01L 21/304 (2006.01); C09J 201/00 (2006.01); B23K 26/364 (2014.01); C09J 7/29 (2018.01); H01L 21/3065 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6836 (2013.01); B23K 26/364 (2015.10); B23K 26/38 (2013.01); C09J 7/29 (2018.01); C09J 201/00 (2013.01); H01L 21/304 (2013.01); H01L 21/3065 (2013.01); H01L 21/78 (2013.01); C09J 2203/326 (2013.01); C09J 2301/414 (2020.08); C09J 2423/046 (2013.01); C09J 2431/006 (2013.01); C09J 2433/006 (2013.01); H01L 2221/68327 (2013.01);
Abstract
A mask-integrated surface protective tape for production of semiconductor chips, with the production containing steps (a) to (d), which tape comprises a base film and a mask material layer provided thereon, wherein a wetting tension of the base film on the side from which the mask material layer has been peeled is from 20.0 mN/m to 48.0 mN/m, and wherein a surface roughness Ra of the base film on the side from which the mask material layer has been peeled is within a range from 0.05 μm to 2.0 μm when measured in conformity to JIS B0601,