The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Mar. 20, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Tadashi Nagahara, Tokyo, JP;

Franklin Antony muthu Sunder, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/34 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/349 (2013.01); G06F 11/10 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01); G11C 16/3431 (2013.01);
Abstract

Disclosed herein is a method and a system for handling read disturb errors in a memory unit. Status information related to each memory block in the memory unit is retrieved and plurality of target memory blocks with valid pages and having highest block erase count are identified for patrolling. Each valid page in the target memory blocks are patrolled for identifying read disturb errors. Finally, each valid page having read disturb errors are recycled, thereby effectively handling the read disturb errors in the memory unit. The method disclosed herein involves patrolling of only the valid pages in the memory block, thereby reducing the time required for handling the read disturb errors and improving the overall performance. Also, the method ensures data retention reliability within each memory blocks by patrolling the memory block in the order of highest block erase counts.


Find Patent Forward Citations

Nagahara, Tadashi. (2021). Performance based method and system for patrolling read disturb errors in a memory unit (U.S. Patent No. 10971241). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10971241

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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