The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Oct. 31, 2019
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jung Hwan Lee, Osan-si, KR;

Jung Mi Ko, Icheon-si, KR;

Ji Hwan Kim, Seoul, KR;

Kwang Ho Baek, Icheon-si, KR;

Young Don Jung, Suwon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 16/34 (2006.01); G11C 16/30 (2006.01); G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01); G11C 16/3409 (2013.01); G11C 16/3459 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01);
Abstract

Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.


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