The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Aug. 08, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Kikuko Sugimae, Mie, JP;

Yusuke Arayashiki, Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0026 (2013.01); G11C 13/004 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 27/2481 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1266 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01); H01L 45/1675 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/11 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); G11C 2213/33 (2013.01); G11C 2213/34 (2013.01); G11C 2213/71 (2013.01); H01L 45/147 (2013.01);
Abstract

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.


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