The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Oct. 30, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Makoto Yabuuchi, Tokyo, JP;

Shinji Tanaka, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 11/412 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/14 (2013.01); G11C 11/412 (2013.01); H01L 27/1108 (2013.01);
Abstract

A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.


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