The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Oct. 26, 2017
Applicants:

Panasonic Corporation, Osaka, JP;

Panasonic Liquid Crystal Display Co., Ltd., Hyogo, JP;

Panasonic Semiconductor Solutions Co., Ltd., Nagaokakyo, JP;

Inventors:

Jun Suzuki, Kanagawa, JP;

Akihiro Yoshizawa, Kanagawa, JP;

Hideki Nozaki, Kanagawa, JP;

Satoshi Endou, Osaka, JP;

Kenji Fukuta, Osaka, JP;

Hiroaki Goto, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G02F 1/133 (2006.01); G02F 1/1362 (2006.01); G09G 3/00 (2006.01); G02F 1/13 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G02F 1/1309 (2013.01); G02F 1/13306 (2013.01); G02F 1/136286 (2013.01); G09G 3/006 (2013.01); G09G 3/20 (2013.01); G02F 2001/136254 (2013.01); G09G 2310/0297 (2013.01); G09G 2330/12 (2013.01); G09G 2380/10 (2013.01);
Abstract

A liquid crystal display includes source lines and gate lines, pixel electrodes, switching elements, a source driver, a gate driver, and a failure inspection circuit. The source lines and the gate lines are disposed in a lattice form. The pixel electrode is disposed in a pixel region defined by the source line and the gate line. The switching element is disposed corresponding to the pixel electrode. The source driver drives the source lines. The gate driver drives the gate lines. The failure inspection circuit is connected to the source lines or the gate lines, and performs inspection of the source lines or the gate lines. The failure inspection circuit includes monitor input signal lines, monitor output signal lines, a determination circuit that detects voltage levels of output signals from the monitor output signal lines, and an expected value comparison circuit that compares outputs from the determination circuit with expected values.


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