The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Feb. 03, 2020
Applicant:

Phison Electronics Corp., Miaoli, TW;

Inventors:

Shih-Yang Sun, Taoyuan, TW;

Sheng-Wen Chen, Taichung, TW;

Yen-Po Lin, Kaohsiung, TW;

Bo-Jing Lin, Hsinchu, TW;

Po-Min Cheng, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 25/03 (2006.01); H03L 7/085 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0058 (2013.01); H03L 7/085 (2013.01); H03L 7/0991 (2013.01); H04L 7/0025 (2013.01); H04L 25/03057 (2013.01);
Abstract

A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.


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