The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Oct. 31, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Xuefeng Liu, Schenectady, NY (US);

Junli Wang, Albany, NY (US);

Brent A. Anderson, Jericho, VT (US);

Terence B. Hook, Jericho, VT (US);

Gauri Karve, Cohoes, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/762 (2013.01); H01L 27/088 (2013.01); H01L 29/1037 (2013.01); H01L 29/41741 (2013.01); H01L 29/41783 (2013.01); H01L 29/6656 (2013.01); H01L 29/66628 (2013.01); H01L 29/66666 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/785 (2013.01); H01L 21/76224 (2013.01);
Abstract

A method for fabricating a semiconductor device includes forming a vertical field-effect transistor (FET) device including a plurality of first fin structures in a vertical FET device area of a substrate, and forming an input/output (IO) FET device including at least two second fin structures in an IO FET device area of the substrate. The at least two fin structures are connected by a channel having a length determined based on at least one voltage for implementing the IO FET device. Forming the vertical FET and IO FET devices includes selectively exposing a portion of the IO FET device area by selectively removing a portion of a first spacer formed on the substrate in the IO FET device area.


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