One-time programmable (otp) memory devices and methods of testing otp memory devices

Abstract

A one-time programmable (OTP) memory device including: a cell array circuit including an OTP cell array and dummy cell block, the OTP cell array includes OTP memory cells coupled to bit-lines, read word-lines and voltage word-lines and the dummy cell block is coupled to the read word-lines and voltage word-lines; a row decoder coupled to the dummy cell block and the OTP cell array through the read word-lines and voltage word-lines; a column decoder coupled to the OTP cell array through the bit-lines; a write-sensing circuit coupled to the column decoder; and a control circuit to control the cell array circuit, row decoder and write-sensing circuit based on a command and address, the cell array circuit further includes an isolation circuit to cut off first and second voltages which are transferred to the OTP cell array from the row decoder, in response to control codes in a test mode.