The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Aug. 03, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sang Wan Nam, Hwaseong-si, KR;

Yong Hyuk Choi, Suwon-si, KR;

Jun Yong Park, Seoul, KR;

Jung No Im, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/16 (2006.01); G11C 16/32 (2006.01); G11C 16/30 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/08 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01);
Abstract

A memory device includes a memory cell region including a metal pad and first and second memory cells in a memory block, a peripheral circuit region including another metal pad and vertically connected to the memory cell region by the metal pads, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region connected to the second memory cell, an address decoder in the peripheral circuit region applying one of an erase voltage and an inhibit voltage to the first and second word lines, and control logic in the peripheral circuit region controlling an erasing operation on the memory block. During the erasing operation the inhibit voltage is applied to the first word line after the erase voltage, and the erase voltage is applied to the second word line after the inhibit voltage.


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