The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2021
Filed:
Aug. 19, 2016
Arm Limited, Cambridge, GB;
Rowan Nigel Naylor, Cambridge, GB;
Phanindra Kumar Mannava, Austin, TX (US);
Bruce James Mathewson, Cambridge, GB;
Arm Limited, Cambridge, GB;
Abstract
An interconnect circuit, and method of operation of such an interconnect circuit, are provided. The interconnect circuitry has a first interface for coupling to a master device and a second interface for coupling to a slave device. Transactions are performed between the master device and the slave device, where each transaction comprises or more transfers, and each transfer comprises a request and a response. A first connection path between the first interface and the second interface is provided that comprises a first plurality of pipeline stages. The first connection path forms a default path for propagation of the requests and responses of the transfers. A second connection path is also provided between the first interface and the second interface that comprises a second plurality of pipeline stages, where the second plurality is less than the first plurality. Path selection circuitry is then used to determine presence of a fast path condition. In the presence of the fast path condition, the path selection circuitry causes at least one of the request and the response for one or more transfers to be propagated via the second connection path. This can significantly reduce the latency associated with the handling of transfers within the interconnect circuitry, and hence improves the overall performance of the interconnect circuitry.