The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2021

Filed:

Feb. 18, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Bryan Lloyd, Austin, TX (US);

Balaram Sinharoy, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/30 (2018.01); G06F 12/1027 (2016.01); G06F 9/34 (2018.01); G06F 12/1009 (2016.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/34 (2013.01); G06F 9/3824 (2013.01); G06F 9/3832 (2013.01); G06F 9/3836 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 9/3834 (2013.01); G06F 9/3851 (2013.01); G06F 2212/65 (2013.01); G06F 2212/68 (2013.01);
Abstract

Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.


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