The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10958487 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 23, 2021

Filed:

Jul. 16, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventor:

Troy James Beukema, Briarcliff Manor, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03878 (2013.01); H04L 25/0264 (2013.01); H04L 25/03114 (2013.01);
Abstract

An apparatus includes an FFE circuit, including a clock generator creating multiple sub-rate phases of an input clock, and a multi-phase sampler responsive to a data signal and to the multiple sub-rate phases generated by the clock generator. The sampler is configured to sample the data signal and to generate held sample outputs corresponding to the multiple sub-rate phases. A SC equalization circuit in the FFE circuit has two states and is responsive to inputs from the multi-phase sampler output and the clock generator. The SC equalization circuit is configured to form outputs using the two states. A variable gain output stage in the FFE circuit is responsive to the outputs from the SC equalization circuit and is responsive to gain control signal(s) to provide variable gains to corresponding outputs of the SC equalization circuit to form equalized outputs based on the data signal.


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