The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Dec. 07, 2018
Applicant:

Imagination Technologies Limited, Kings Langley, GB;

Inventors:

Christopher Owen, Stroud, GB;

Adrian John Anderson, Chepstow, GB;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1111 (2013.01); H03M 13/114 (2013.01); H03M 13/1114 (2013.01); H03M 13/1137 (2013.01); H03M 13/1165 (2013.01); H03M 13/611 (2013.01); H03M 13/6516 (2013.01); H03M 13/6566 (2013.01);
Abstract

Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P(where P≥P) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P*q bits.


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