The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
Mar. 26, 2019
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Rishi Soundararajan, Bengaluru, IN;
Visvesvaraya Pentakota, Bengaluru, IN;
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/24 (2006.01); H03M 1/50 (2006.01); H03K 5/00 (2006.01); H03M 1/36 (2006.01); H03M 1/46 (2006.01); H03M 1/48 (2006.01);
U.S. Cl.
CPC ...
H03K 5/249 (2013.01); H03M 1/50 (2013.01); H03K 2005/00215 (2013.01); H03M 1/36 (2013.01); H03M 1/46 (2013.01); H03M 1/48 (2013.01);
Abstract
A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.