The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Jun. 08, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Chiemi Hashimoto, Tokyo, JP;

Kosuke Yayama, Tokyo, JP;

Katsumi Tsuneno, Tokyo, JP;

Tomokazu Matsuzaki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H03K 3/011 (2006.01); H01L 23/522 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01); H03K 3/356 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H03K 3/011 (2013.01); H01L 23/5226 (2013.01); H01L 23/5228 (2013.01); H01L 27/0802 (2013.01); H01L 28/20 (2013.01); H03K 3/356113 (2013.01); H01L 23/53266 (2013.01); H01L 23/53271 (2013.01);
Abstract

A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.


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