The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Feb. 27, 2020
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Mojtaba Ashourloo, Toronto, CA;

Venkata Raghuram Namburi, Brampton, CA;

Gerard Villar Piqué, Eindhoven, NL;

John Pigott, Phoenix, AZ;

Olivier Trescases, Toronto, CA;

Hendrik Bergveld, Eindhoven, NL;

Alaa Eldin Y El Sherif, Plano, TX (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/00 (2006.01); H02M 3/00 (2006.01); H02M 1/32 (2007.01);
U.S. Cl.
CPC ...
H02M 1/00 (2013.01); H02M 3/00 (2013.01); H02M 2001/008 (2013.01); H02M 2001/325 (2013.01);
Abstract

Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.


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