The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Feb. 07, 2020
Applicants:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Toshiba Electronic Devices & Storage Corporation, Minato-ku, JP;

Inventor:

Kenichi Matsushita, Nonoichi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/43 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/73 (2006.01); H01L 29/49 (2006.01); H01L 29/76 (2006.01); H01L 29/737 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 29/0692 (2013.01); H01L 29/435 (2013.01); H01L 29/49 (2013.01); H01L 29/6659 (2013.01); H01L 29/66242 (2013.01); H01L 29/66265 (2013.01); H01L 29/66272 (2013.01); H01L 29/66325 (2013.01); H01L 29/7302 (2013.01); H01L 29/7371 (2013.01); H01L 29/7393 (2013.01); H01L 29/7395 (2013.01); H01L 29/7397 (2013.01); H01L 29/76 (2013.01); H01L 29/783 (2013.01); H01L 29/7816 (2013.01); H01L 29/7833 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first ring-shaped region, a second ring-shaped region, a second electrode, a third electrode, a first conductive layer, and a semi-insulating layer. The first ring-shaped region surrounds the second semiconductor region, and is provided between the second and third semiconductor regions. The second ring-shaped region surrounds the first ring-shaped region, and is provided between the first ring-shaped region and the third semiconductor region. The first conductive layer surrounds the second electrode, and is provided on the first ring-shaped region, the second ring-shaped region, and a first region of the first semiconductor region with an insulating layer interposed. The first region is positioned between the first and second ring-shaped regions. The semi-insulating layer contacts the second electrode, the first conductive layer, and the third electrode.


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