The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Dec. 18, 2019
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Dmitry Yakimets, Leuven, BE;

Anshul Gupta, Leuven, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/74 (2006.01); H01L 21/311 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/743 (2013.01); H01L 21/31144 (2013.01); H01L 21/481 (2013.01); H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 23/3107 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01);
Abstract

An integrated circuit chip having fin-based active devices in the front end of line, and an electrical connection between a buried interconnect rail and a contact area on a semiconductor fin, such as an epitaxially grown source or drain contact area of a transistor, is disclosed. In one aspect, the electrical connection is realized without the intervention of a metallization level formed above the active devices in the IC. Instead, an interconnect via is produced between the buried interconnect rail and a lateral portion of the contact area, wherein the lateral portion is directly contacted by a sidewall of the interconnect via. Methods for producing the interconnect via are also disclosed.


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