The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Oct. 18, 2019
Applicant:

SK Hynix Inc., Icheon, KR;

Inventors:

Sun Young Kim, Andong, KR;

Nam Jae Lee, Cheongju, KR;

Assignee:

SK hynix Inc., Icheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/82 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02595 (2013.01); H01L 21/0254 (2013.01); H01L 21/02178 (2013.01); H01L 21/02532 (2013.01); H01L 21/02554 (2013.01); H01L 21/82 (2013.01); H01L 27/0688 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming a first sacrificial layer including a nitride over a first source layer, forming a second sacrificial layer including aluminum oxide over the first sacrificial layer, forming a second source layer over the second sacrificial layer, forming a stacked structure over the second source layer, forming a channel layer that passes through the stacked structure, the second source layer, the second sacrificial layer, and the first sacrificial layer, the channel layer being enclosed by a memory layer, forming a slit that passes through the stacked structure and the second source layer, forming a polysilicon spacer in the slit, forming an opening by removing the first sacrificial layer and the second sacrificial layer, exposing the channel layer by etching the memory layer, and forming a third source layer in the opening.


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