The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2021

Filed:

Sep. 11, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Akio Sugahara, Yokohama Kanagawa, JP;

Takaya Handa, Yokohama Kanagawa, JP;

Ryosuke Isomura, Matsudo Chiba, JP;

Kazuto Uehara, Sagamihara Kanagawa, JP;

Junichi Sato, Yokohama Kanagawa, JP;

Norichika Asaoka, Yokohama Kanagawa, JP;

Masashi Yamaoka, Yokohama Kanagawa, JP;

Bushnaq Sanad, Yokohama Kanagawa, JP;

Yuzuru Shibazaki, Fujisawa Kanagawa, JP;

Noriyasu Kumazaki, Kawasaki Kanagawa, JP;

Yuri Terada, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/30 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/12 (2006.01); G11C 16/32 (2006.01); G11C 16/08 (2006.01); H01L 27/115 (2017.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/32 (2013.01); G11C 16/12 (2013.01); G11C 16/26 (2013.01); H01L 27/115 (2013.01);
Abstract

According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.


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